Devices get turned on and off. When a device is turned on, power may not be instantaneously available to every component in the device. Even when power is available, it may not be available at a desired level for component operation. When a component on a device is an integrated circuit, it may be valuable to hold the integrated circuit in a reset condition until stable (e.g., fully ramped up) power is available at a desired level. Integrated circuits may be held in reset until they receive a power on reset signal from a power on reset circuit.
Traditional power on reset circuits are analog circuits that produce a constant power drain, even after performing their role in holding components in reset and then asserting a power on reset signal. A constant power drain is undesirable in a battery powered device. Traditional power on reset circuits can be difficult to port from device to device because different devices have different amounts of power available, have different power ramp characteristics, and/or consume different amounts of power during reset. For example, one device can have a power ramp measured in microseconds while another device has a power ramp measured in milliseconds.
FIG. 1 illustrates a power signal 100 that starts at a low level and that ramps up during a power ramp period 110. A power on reset signal 120 is held low during a power on reset delay time period 130. When a device is powered up, integrated circuits and/or other components on the device can be held in a reset state until power has ramped up to a desired state. The period of time for which the integrated circuits and/or other components are held in reset may vary. The exact time for which integrated circuits and/or other components are held in reset is generally not finely controllable and yet a device or devices still need to be held in reset for a minimum period of time. However, allowing a component to begin operations prematurely, (e.g., before power is in desired state), can have undesirable side effects.
Therefore, it would be desirable to have a power on circuit that does not produce a constant power drain and that can guarantee that at least a minimum time period elapses when a device is powered up to facilitate having components begin operations at a favorable time.